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Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 100-Pin TQFP Commercial Temp Industrial Temp Features
* FT pin for user-configurable flow through or pipeline operation * Single Cycle Deselect (SCD) operation * 1.8 V +10%/-10% core power supply * 1.8 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to Interleaved Pipeline mode * Byte Write (BW) and/or Global Write (GW) operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 100-lead TQFP package
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
350 MHz-150 MHz 1.8 V VDD 1.8 V I/O
cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edgetriggered Data Output Register.
Functional Description
Applications
The GS8160V18/32/36AT is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst
Core and Interface Voltages
The GS8160V18/32/36AT operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.
Parameter Synopsis
-350 Pipeline 3-1-1-1 tKQ tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) 1.8 2.85 395 455 4.5 4.5 270 305 -333 2.0 3.0 370 430 4.7 4.7 250 285 -300 2.2 3.3 335 390 5.0 5.0 230 270 -250 2.3 4.0 280 330 5.5 5.5 210 240 -200 2.7 5.0 230 270 6.5 6.5 185 205 -150 3.3 6.7 185 210 7.5 7.5 170 190 Unit ns ns mA mA ns ns mA mA
Flow Through 2-1-1-1
Rev: 1.00a 6/2003
1/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
GS8160V18A 100-Pin TQFP Pinout
VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB6 VDD VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
Rev: 1.00a 6/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A 2/24 (c) 2003, Giga Semiconductor, Inc.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
GS8160V32A 100-Pin TQFP Pinout
NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD3 DQD DQD DQD VSS VDDQ DQD DQD NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A
NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC
Rev: 1.00a 6/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A 3/24 (c) 2003, Giga Semiconductor, Inc.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
GS8160V36A 100-Pin TQFP Pinout
DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A
DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA
Rev: 1.00a 6/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A 4/24 (c) 2003, Giga Semiconductor, Inc.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
TQFP Pin Description Symbol
A0, A1 A DQA DQB DQC DQD BW BA, BB, BC, BD CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ NC
Type
I I I/O I I I I I I I I I I I I I I I --
Description
Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pins Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect
Rev: 1.00a 6/2003
5/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
GS8160V18/32/36A Block Diagram
Register
A0-An
D
Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1
A
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q D
Register
D BB
Q
36 4
36
Register
D BC
Q Q
Register
D
Register
Q
Register
D
D BD
Q
Register
D
Q
E1 E2 E3
Register
D
Q
Register
D
Q
FT G Power Down Control
ZZ
1
DQx1-DQx9
Note: Only x36 version shown for simplicity.
Rev: 1.00a 6/2003
6/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Pin Name
LBO FT ZZ
State
L H L H or NC L or NC H
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB
Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 01 10 11 00 10 11 00 01 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00a 6/2003
7/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Byte Write Truth Table Function
Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x32 and x36 versions.
Rev: 1.00a 6/2003
8/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Synchronous Truth Table Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None None None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
X X X R R W CR CR CW CW
E1
H L L L L L X H X H X H X H
E2
X F F T T T X X X X X X X X
ADSP ADSC
X L H L H H H X H X H X H X L X L X L L H H H H H H H H
ADV
X X X X X X L L L L H H H H
W3
X X X X F T F F T T F F T T
DQ4
High-Z High-Z High-Z Q Q D Q Q D D Q Q D D
Notes: 1. X = Don't Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00a 6/2003
9/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Simplified State Diagram
X
Deselect W W Simple Synchronous Operation R R
X CW
First Write
R CR
First Read
X CR
Simple Burst Synchronous Operation
W R X Burst Write CR CW
R
Burst Read
X
CR
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low.
Rev: 1.00a 6/2003
10/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Simplified State Diagram with G
X
Deselect W W X W CW R R
First Write
R CR
First Read
X CR
CW
W X Burst Write R CR W CW
R X
Burst Read
CW
CR
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time.
Rev: 1.00a 6/2003
11/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 3.6 -0.5 to 3.6 -0.5 to VDDQ +0.5 ( 3.6 V max.) -0.5 to VDD +0.5 ( 3.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V mA mA W
o o
C C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Rev: 1.00a 6/2003
12/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Power Supply Voltage Ranges Parameter
1.8 V Supply Voltage 1.8 V VDDQ I/O Supply Voltage
Symbol
VDD1 VDDQ1
Min.
1.6 1.6
Typ.
1.8 1.8
Max.
2.0 2.0
Unit
V V
Notes
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
0.6*VDD -0.3 0.6*VDD -0.3
Typ.
-- -- -- --
Max.
VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD
Unit
V V V V
Notes
1 1 1,3 1,3
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
Notes
2 2
Note: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.00a 6/2003
13/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Undershoot Measurement and Timing
VIH VDD + 2.0 V VSS 50% VSS - 2.0 V 20% tKC VIL 50% VDD
Overshoot Measurement and Timing
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
Output Load 1 DQ 50 VDDQ/2 * Distributed Test Jig Capacitance 30pF*
Rev: 1.00a 6/2003
14/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current FTInput Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL IIN1 IIN2 IOL VOH VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -4 mA, VDDQ = 1.6 V IOL = 4 mA, VDD = 1.6 V
Min
-1 uA -1 uA -1 uA -100 uA -1 uA -1 uA VDDQ - 0.4 V --
Max
1 uA 1 uA 100 uA 1 uA 1 uA 1 uA -- 0.4 V
Rev: 1.00a 6/2003
15/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-350 Mode Symbol 0 to 70C -40 to 85C Unit
410 55 280 35 370 35 260 20 50 50 95 75 70 75 60 65 90 95 85 90 85 60 40 50 40 50 40 50 90 65 40 50 40 50 40 50 40 40 75 50 235 15 245 15 215 15 225 15 200 10 210 10 175 10 185 10 50 50 80 55 340 30 350 30 310 25 320 25 260 20 270 20 215 15 225 15 255 30 265 30 240 30 250 30 220 20 230 20 190 15 200 15 175 15 170 15 160 10 40 40 60 50 380 50 390 50 345 45 355 45 290 40 300 40 240 30 250 30 190 20 200 20 185 15 180 15 170 10 50 50 65 55 mA mA mA mA mA mA mA mA
-333 0 to 70C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C 0 to 70C 0 to 70C 0 to 70C 0 to 70C
-300
-250
-200
-150
Rev: 1.00a 6/2003
(x32/ x36) Flow Through 270 35 360 35 250 20 40 40 90 70 Pipeline (x18) Flow Through Pipeline -- Flow Through ISB IDD IDD Pipeline -- Flow Through ISB IDD IDDQ IDD IDDQ IDD IDDQ Pipeline IDD IDDQ 400 55
Parameter
Test Conditions
Operating Current
Device Selected; All other inputs VIH or VIL Output open
Standby Current
ZZ VDD - 0.2 V
16/24
Deselect Current
Device Deselected; All other inputs VIH or VIL
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
(c) 2003, Giga Semiconductor, Inc.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 AC Electrical Characteristics
Parameter
Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery
Symbol
tKC tKQ tKQX tLZ1 tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE tOLZ
1
-350
Min 2.85 -- 1.0 1.0 1.0 0.1 4.5 -- 3.0 3.0 1.3 0.3 1.0 1.2 1.0 -- 0 -- 5 1 20 Max -- 1.8 -- -- -- -- -- 4.5 -- -- -- -- -- -- 1.8 1.8 -- 1.8 -- -- -- 3.0 -- 1.0 1.0 1.0 0.1 4.7 -- 3.0 3.0 1.4 0.4 1.0 1.2 1.0 -- 0 -- 5 1 20
-333
Min Max -- 2.0 -- -- -- -- -- 4.7 -- -- -- -- -- -- 2.0 2.0 -- 2.0 -- -- -- 3.3 -- 1.0 1.0 1.0 0.1 5.0 -- 3.0 3.0 1.4 0.4 1.3 1.5 1.0 -- 0 -- 5 1 20
-300
Min Max -- 2.2 -- -- -- -- -- 5.0 -- -- -- -- -- -- 2.2 2.2 -- 2.2 -- -- -- 4.0 -- 1.0 1.0 1.2 0.2 5.5 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.0 -- 0 -- 5 1 20
-250
Min Max -- 2.3 -- -- -- -- -- 5.5 -- -- -- -- -- -- 2.3 2.3 -- 2.3 -- -- -- 5.0 -- 1.0 1.0 1.4 0.4 6.5 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.0 -- 0 -- 5 1 20
-200
Min Max -- 2.7 -- -- -- -- -- 6.5 -- -- -- -- -- -- 2.7 2.7 -- 2.7 -- -- -- Min 6.7 -- 1.0 1.0 1.5 0.5 7.5 -- 3.0 3.0 1.5 0.5 1.5 1.7 1.0 -- 0 -- 5 1 20
-150
Max -- 3.3 -- -- -- -- -- 7.5 -- -- -- -- -- -- 3.0 3.3 -- 3.0 -- -- --
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Pipeline
Flow Through
tOHZ1 tZZS2 tZZH2 tZZR
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.00a 6/2003
17/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipeline Mode Timing
Read A Single Read Single Write tKL tKH tKC Burst Read Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect
Rev: 1.00a 6/2003
tS tH
ADSC initiated read
Begin
CK
ADSP
ADSC tS tH
ADV tS tH
A B C
A0-An tS
18/24
tS tH tH tS tS tH tS tH
E2 and E3 only sampled with ADSP and ADSC
GW
BW
Ba-Bd
Deselected with E1 E1 masks ADSP
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tS tH tS tOE tOHZ
Q(A) D(B)
E1
E2
E3
G tH tLZ tKQ
Q(C) Q(C+1) Q(C+2) Q(C+3)
tKQX
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
(c) 2003, Giga Semiconductor, Inc.
DQa-DQd
Flow Through Mode Timing
Read A tKL tKH tKC Cont Cont1 Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont2 Deselect
Begin
Rev: 1.00a 6/2003
Fixed High
CK
ADSP tS tH tH ADSC initiated read tH tS tS
ADSC
ADV tS tH
A B C
A0-An tS tH
19/24
tS tH tH tS tS tH tS tH
E2 and E3 only sampled with ADSC
GW
BW
Ba-Bd
Deselected with E1
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tS tH tS tOE
Q(A)
E1
E2
E3
G tOHZ
D(B)
tH
tKQ tLZ
Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tHZ tKQX
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
(c) 2003, Giga Semiconductor, Inc.
DQa-DQd
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tS tH
tKC
tKH tKL
ADSP ADSC
tZZS
ZZ
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
Rev: 1.00a 6/2003
20/24
~~ ~~
tZZH
~ ~
tZZR
~~ ~~
CK
~ ~~~~ ~ ~ ~~~~ ~
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 TQFP Package Drawing
L Symbol
A1 A2 b c D D1 E E1 e L L1 Y
c Pin 1
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom. Max
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 -- 0.45 -- 0.10 1.40 0.30 -- 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 -- 0.75 -- 0.10
L1
e b
D D1
A1
Y
A2
E1 E
0
--
7
Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion.
Rev: 1.00a 6/2003
21/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Ordering Information for GSI Synchronous Burst RAMs
Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32
Part Number1
GS8160V18AT-350 GS8160V18AT-333 GS8160V18AT-300 GS8160V18AT-250 GS8160V18AT-200 GS8160V18AT-150 GS8160V32AT-350 GS8160V32AT-333 GS8160V32AT-300 GS8160V32AT-250 GS8160V32AT-200 GS8160V32AT-150 GS8160V36AT-350 GS8160V36AT-333 GS8160V36AT-300 GS8160V36AT-250 GS8160V36AT-200 GS8160V36AT-150 GS8160V18AT-350I GS8160V18AT-333I GS8160V18AT-300I GS8160V18AT-250I GS8160V18AT-200I GS8160V18AT-150I GS8160V32AT-350I GS8160V32AT-333I GS8160V32AT-300I GS8160V32AT-250I GS8160V32AT-200I GS8160V32AT-150I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP
Speed2 (MHz/ns)
350/4.5 333/4.7 300/5 250/5.5 200/6.5 150/7.5 350/4.5 333/4.7 300/5 250/5.5 200/6.5 150/7.5 350/4.5 333/4.7 300/5 250/5.5 200/6.5 150/7.5 350/4.5 333/4.7 300/5 250/5.5 200/6.5 150/7.5 350/4.5 333/4.7 300/5 250/5.5 200/6.5 150/7.5
TA3
C C C C C C C C C C C C C C C C C C I I I I I I I I I I I I
Status
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8160V18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00a 6/2003 22/24 (c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
Org
512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36
Part Number1
GS8160V36AT-350I GS8160V36AT-333I GS8160V36AT-300I GS8160V36AT-250I GS8160V36AT-200I GS8160V36AT-150I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP
Speed2 (MHz/ns)
350/4.5 333/4.7 300/5 250/5.5 200/6.5 150/7.5
TA3
I I I I I I
Status
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8160V18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00a 6/2003
23/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8160V18/32/36AT-350/333/300/250/200/150
18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New
GS8160VxxA_r1
Types of Changes Format or Content
Page;Revisions;Reason
* Creation of new datasheet
Rev: 1.00a 6/2003
24/24
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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